Intel said the new design creates a stack of central processing unit, graphics processing unit.
Intel has dropped new information about its new tile-based chip packaging design at Hot Chips, an industry event on semiconductors. The new design has been used in Intel’s upcoming Meteor Lake, Arrow Lake, and Lunar Lake processors.
Intel said that the new design creates a stack of central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), and I/O tiles using the company’s Foveros interconnect technology. It is based on the open Universal Chiplet Interconnect Express (UCIe) specification that makes chiplets designed and manufactured on different process technologies by different vendors compatible with each other.
System-on-chip, and I/O tiles using the company’s Foveros interconnect free robux web technology.
UCIe is an open standard created to encourage the wider adoption of chiplet-based CPUs. Earlier this year, Intel, Apple, ARM, Samsung, and Google created an industry consortium to promote UCIe.
Meteor Lake is going to be Intel’s first chiplet based product and is expected to launch sometime this year.
Chiplet-based CPUs have a modular design that combines multiple smaller dies to create a single CPU package. It is being done because incorporating more transistors on a single die is becoming a challenge. Apple’s new M1 Ultra chip, launched at the Spring event in March, is also based on a chiplet design.
Further, Intel also previewed its new GPU for data centers. Its code-named Ponte Vecchio and is designed to address the compute density in high-performance computing (HPC) and artificial intelligence (AI) driven supercomputing workloads.
Ponte Vecchio is also based on the new tile-based design and uses embedded multi-die interconnect bridge (EMIB) and Foveros advanced packaging technologies. Intel claims a single package of the new GPU contains more than 100 billion transistors.